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INTEGRATED CIRCUITS
DATA SHEET
74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state
Product specification File under Integrated Circuits, IC06 1999 Jun 16
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FEATURES * 3-state non-inverting outputs for bus oriented applications * 8-bit positive, edge-triggered register * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V * Independent register and 3-state buffer operation * Common 3-state output enable input * Output capability; bus driver * ICC category: MSI * For AHC only: operates with CMOS input levels * For AHCT only: operates with TTL input levels * Specified from -40 to +85 and +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 3.0 ns. DESCRIPTION
74AHC574; 74AHCT574
The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The `574' is functionally identical to the `564', but has non-inverting outputs. The `574' is functionally identical to the `374', but has a different pinning.
TYPICAL SYMBOL tPHL/tPLH fmax CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 1999 Jun 16 2 PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CL = 15 pF; VCC = 5 V VI = VCC or GND 130 4.0 4.0 10 130 4.0 4.0 12 MHz pF pF pF CONDITIONS AHC CL = 15 pF; VCC = 5 V 4.4 AHCT 4.4 ns UNIT
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FUNCTION TABLE See note 1. INPUTS OPERATING MODES OE Load and read register Load register and disable outputs L L H H Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; = LOW-to-HIGH CP transition. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC574D 74AHC574PW 74AHCT574D 74AHCT574PW PINNING PIN 1 2, 3, 4, 5, 6, 7, 8 and 9 10 11 19, 18, 17, 16, 15, 14, 13 and 12 20 OE D0 to D7 GND CP Q0 to Q7 VCC SYMBOL data inputs ground (0 V) PACKAGES NORTH AMERICA PINS 74AHC574D 74AHC574PW DH 74AHCT574D 74AHCT574PW DH 20 20 20 20 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CP Dn I h l h
74AHC574; 74AHCT574
INTERNAL FLIP-FLOPS L H L H
OUTPUTS Q0 to Q7 L H Z Z
CODE SOT163-1 SOT360-1 SOT163-1 SOT360-1
DESCRIPTION 3-state output enable input (active LOW)
clock input (LOW-to-HIGH, edge triggered) 3-state flip-flop outputs DC supply voltage
1999 Jun 16
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574; 74AHCT574
handbook, halfpage
OE 1 D0 2 D1 3 D2 4 D3 5
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3
handbook, halfpage
11 2 3 4 5 6 7 8 9 CP D0 D1 D2 D3 D4 D5 D6 D7 OE 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12
574
D4 6 D5 7 D6 8 D7 9 GND 10
MNA444
15 Q4 14 Q5 13 Q6 12 Q7 11 CP
MNA445
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
11 1
C1 EN
handbook, halfpage
2 3 19 18 17 16 15 14 13 12
MNA446
D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 3-STATE OUTPUTS
Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12
2 3 4 5 6 7 8 9
1D
4 5 6 7 8 9
11 CP 1 OE
MNA447
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
1999 Jun 16
4
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D0 D1 D2 D3 D Q FF1 CP D Q FF2 CP D Q FF3 CP D FF4 CP
Philips Semiconductors
Q
handbook, full pagewidth
Octal D-type flip-flop; positive edge-trigger; 3-state
D4
D5
D6
D7
D
Q FF5
D
Q FF6
D FF7 CP
Q
D
Q FF8
CP
CP
CP
5
CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MNA449
74AHC574; 74AHCT574
Product specification
Fig.5 Logic diagram.
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb tr,tf (t/f) PARAMETER DC supply voltage input voltage output voltage operating ambient temperature range input rise and fall times except for Schmitt-trigger inputs see DC and AC characteristics per device VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40 - - TYP. 5.0 - - +25 +25 - - MAX. 5.5 5.5 VCC +85 +125 100 20 MIN. 4.5 0 0 -40 -40 - -
74AHC574; 74AHCT574
74AHCT UNIT TYP. 5.0 - - +25 +25 - - MAX. 5.5 5.5 VCC +85 +125 - 20 V V V C C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO-packages: above 70 C the value of PD derates linearly with 8 mW/K. For TSSOP-packages: above 60 C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage range DC input diode current DC output diode current DC output source or sink current DC VCC or GND current storage temperature range power dissipation per package for temperature range: -40 to +125 C; note 2 VI < -0.5 V; note 1 VO < -0.5 V or VO > VCC + 0.5 V; note 1 -0.5 V < VO < VCC + 0.5 V CONDITIONS MIN. -0.5 -0.5 - - - - -65 - MAX. +7.0 +7.0 -20 20 25 75 +150 500 UNIT V V mA mA mA mA C mW
1999 Jun 16
6
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
DC CHARACTERISTICS Family 74AHC Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage; all outputs HIGH-level output voltage VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -4.0 mA VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage; all outputs LOW-level output voltage VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 4.0 mA VI = VIH or VIL; IO = 8.0 mA II IOZ ICC CI input leakage current 3-state output OFF current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 - - - 1.9 2.9 4.4 - - - - - 2.0 3.0 4.5 +25 TYP. - - - 0.5 0.9 1.65 - - - - - 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (C) -40 to +85 - - 0.5 0.9 1.65 - - -
74AHC574; 74AHCT574
-40 to +125 UNIT - - 0.5 0.9 1.65 - - - V V V
MAX. MIN. MAX. MIN. MAX. 1.5 2.1 - - - 1.9 2.9 4.4 1.5 2.1 - - - 1.9 2.9 4.4 V
3.85 -
3.85 -
3.85 -
2.58 - 3.94 - - - - - - - - - - 0 0 0 - - - - - 3
2.48 - 3.8 - - - - - - - 0.1 0.1 0.1 0.44 0.44 1.0 2.5 40 10
2.40 - 3.70 - - - - - - - - - - 0.1 0.1 0.1 0.55 0.55 2.0
V
V
A
VI = VIH or VIL; 5.5 VO = VCC or GND VI = VCC or GND; IO = 0 5.5 -
0.25 - 4.0 10 - -
10.0 A 80 10 A pF
1999 Jun 16
7
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
Family 74AHCT Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage; all outputs HIGH-level output voltage VOL LOW-level output voltage; all outputs LOW-level output voltage II IOZ input leakage current 3-state output OFF current VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -8.0 mA VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 8.0 mA VI = VIH or VIL VI = VIH or VIL; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; IO = 0 VI = VCC - 2.1 V other inputs at VCC or GND; IO = 0 VCC (V) +25 - - 4.5 - 0.8 - Tamb (C) -40 to +85 - 0.8 -
74AHC574; 74AHCT574
-40 to +125 UNIT - 0.8 -
MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 - 4.4 2.0 - 4.4 V V V
4.5 to 5.5 2.0 4.5 to 5.5 - 4.5 4.4
4.5 4.5
3.94 - - 0
- 0.1
3.8 -
- 0.1
3.70 - - 0.1
V V
4.5 5.5 5.5
- - -
- - -
0.36 0.1
- -
0.44 1.0 2.5
- - -
0.55 2.0
V A
0.25 -
10.0 A
ICC ICC
quiescent supply current additional quiescent supply current per input pin input capacitance
5.5
-
- -
4.0 1.35
- -
40 1.5
- -
80 1.5
A mA
4.5 to 5.5 -
CI
-
-
3
10
-
10
-
10
pF
1999 Jun 16
8
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
AC CHARACTERISTICS Type 74AHC574 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn see Figs 6, 8 and 9 see Figs 7 and 9 50 pF see Figs 6, 8 and 9 see Figs 7 and 9 see Figs 6, 8 and 9 see Figs 7 and 9 50 pF see Figs 6, 8 and 9 see Figs 7 and 9 CL VCC (V) 15 pF 3.0 to 3.6 - +25 MIN. TYP. Tamb (C) -40 to +85
74AHC574; 74AHCT574
-40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX. 1.0 15.5 1.0 16.5 ns
6.5(1) 13.2
tPZH/tPZL
-
5.7(1) 12.8
1.0
15.0
1.0
16.0
ns
tPHZ/tPLZ
-
6.3(1) 13.0
1.0
15.0
1.0
16.5
ns
tPHL/tPLH
-
9.3(1) 16.7
1.0
19.0
1.0
21.0
ns
tPZH/tPZL
-
8.2(1) 16.3
1.0
18.5
1.0
20.5
ns
tPHZ/tPLZ
-
9.1(1) 15.0
1.0
17.0
1.0
19.0
ns
tPHL/tPLH
15 pF 4.5 to 5.5 -
4.4(2) 8.6
1.0
10.0
1.0
11.0
ns
tPZH/tPZL
-
4.2(2) 9.0
1.0
10.5
1.0
11.5
ns
tPHZ/tPLZ
-
4.3(2) 9.0
1.0
10.5
1.0
11.5
ns
tPHL/tPLH
-
6.2(2) 10.6
1.0
12.0
1.0
13.5
ns
tPZH/tPZL
-
5.9(2) 11.0
1.0
12.5
1.0
14.0
ns
tPHZ/tPLZ
-
6.9(2) 10.1
1.0
11.5
1.0
13.0
ns
1999 Jun 16
9
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574; 74AHCT574
Tamb (C)
TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tW clock pulse see Figs 6 width and 9 HIGH or LOW setup time Dn to CP hold time Dn to CP maximum clock pulse frequency see Figs 6 and 9 15 pF see Figs 8 and 9 CL VCC (V) +25 MIN. TYP. - -
-40 to +85 -
-40 to +125 UNIT -
MAX. MIN. MAX. MIN. MAX. 5.0 5.0 ns
50 pF 3.0 to 3.6 5.0
tsu th fmax
3.5 1.5 50 80
- - 75 125 -
- - - - -
3.5 1.5 45 65 5.0
- - - - -
3.5 1.5 45 65 5.0
- - - - -
ns ns MHz MHz ns
tW
clock pulse see Figs 6 width and 9 HIGH or LOW setup time Dn to CP hold time Dn to CP maximum clock pulse frequency see Figs 6 and 9 see Figs 8 and 9
50 pF 4.5 to 5.5 5.0
tsu th fmax
3.0 1.5 85 15 pF 130
- - 115 180
- - - -
3.0 1.5 75 110
- - - -
3.0 1.5 75 110
- - - -
ns ns MHz MHz
Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V.
1999 Jun 16
10
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
Type 74AHCT574 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn clock pulse see Figs 6 width and 9 HIGH or LOW setup time Dn to CP hold time Dn to CP maximum clock pulse frequency see Figs 6 and 9 15 pF see Figs 8 and 9 see Figs 6 and 9 see Figs 7 and 9 50 pF see Figs 6 and 9 see Figs 7 and 9 CL VCC (V) 15 pF 4.5 to 5.5 - +25 MIN. TYP. 4.4(1) Tamb (C) -40 to +85
74AHC574; 74AHCT574
-40 to +125 UNIT MAX. 11.0 ns
MAX. MIN. MAX. MIN. 8.6 1.0 10.0 1.0
tPZH/tPZL
-
4.3(1) 9.0
1.0
10.5
1.0
11.5
ns
tPHZ/tPLZ
-
4.3(1) 9.0
1.0
10.5
1.0
11.5
ns
tPHL/tPLH
-
6.3(1) 10.6
1.0
12.0
1.0
13.5
ns
tPZH/tPZL
-
6.1(1) 11.0
1.0
12.5
1.0
14.0
ns
tPHZ/tPLZ
-
6.2(1) 10.1
1.0
11.5
1.0
13.0
ns
tW
5.0
-
-
5.5
-
5.5
-
ns
tsu th fmax
3.0 1.5 85 130
- - 115 180
- - - -
3.5 1.5 75 110
- - - -
3.5 1.5 75 110
- - - -
ns ns MHz MHz
Note 1. Typical values at VCC = 5.0 V.
1999 Jun 16
11
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
AC WAVEFORMS
74AHC574; 74AHCT574
handbook, full pagewidth
1/f max VI CP INPUT GND tW tPHL tPLH VM(1)
Qn OUTPUT
VM(1)
MNA200
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
Fig.6 The clock (CP) to output (Qn) propagation delays.
handbook, full pagewidth
VI OE INPUT GND tPLZ OUTPUT LOW-to-OFF OFF-to-LOW VCC VM VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
MNA450
VM(1)
tPZL
VOL + 0.3 V tPZH VOH - 0.3 V VM
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
Fig.7 The 3-state enable and disable times.
1999 Jun 16
12
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574; 74AHCT574
handbook, full pagewidth
VI CP INPUT GND t su th VI Dn INPUT GND
MNA448
VM(1)
t su th
VM(1)
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig.8 The data set-up and hold times for Dn input.
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL
MNA183
VO
1000
VCC open GND
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND
S1
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM INPUT 50% VCC 1.5 V
VM OUTPUT 50% VCC 50% VCC
Fig.9 Load circuitry for switching times.
1999 Jun 16
13
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm
74AHC574; 74AHCT574
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
ISSUE DATE 95-01-24 97-05-22
1999 Jun 16
14
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574; 74AHCT574
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153AC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-06-16 95-02-04
1999 Jun 16
15
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
74AHC574; 74AHCT574
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Jun 16
16
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable
74AHC574; 74AHCT574
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Jun 16
17
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
NOTES
74AHC574; 74AHCT574
1999 Jun 16
18
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
NOTES
74AHC574; 74AHCT574
1999 Jun 16
19
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 66
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/01/pp20
Date of release: 1999 Jun 16
Document order number:
9397 750 06027

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